Despite the name "Random Access Memory," accessing DRAM is anything but uniform. The memory controller — once a separate chip, now integrated into the CPU since Intel's Nehalem (2008) and AMD's K8 (2003) — must navigate a minefield of timing constraints dictated by the physical structure of DRAM.

DRAM is a grid, not a flat array. Each DRAM chip is organized into banks, rows, and columns. A bank contains a row buffer (typically 8KB) that acts like a single-row cache. Accessing memory follows a three-step dance:

• ACTIVATE (RAS): Open a row, copying it into the row buffer. This takes tRCD (Row-to-Column Delay), around 14ns on DDR5-5600.
• READ/WRITE (CAS): Access a column within the open row. This takes CL (CAS Latency), around 14ns on the same module.
• PRECHARGE: Close the row before opening a different one in the same bank. This takes tRP, again roughly 14ns.

This gives three access scenarios with very different latencies:

• Row buffer hit: Target row already open. Cost = CL only (~14ns). This is the fast path.
• Row buffer miss (empty): No row open. Cost = tRCD + CL (~28ns).
• Row buffer conflict: Wrong row open. Cost = tRP + tRCD + CL (~42ns). This is the worst case — three times slower than a hit.

The memory controller's job is to minimize conflicts. It does this through request reordering. Modern controllers use an FR-FCFS (First-Ready, First-Come-First-Served) policy: prioritize requests that hit the currently open row, regardless of arrival order. This is why sequential memory access patterns dramatically outperform random access — they keep hitting the same row buffer.

Rule of thumb: A single DDR5-5600 channel delivers ~45 GB/s peak bandwidth, but random 64-byte access across banks yields roughly 1–2 GB/s effective throughput. Sequential access can get within 80% of peak; random access may achieve only 3–5%.

Bank parallelism is the escape hatch. DDR5 doubles the bank groups from DDR4 (8 to 16 per channel) and splits each channel into two independent 32-bit subchannels. The controller can pipeline ACTIVATE to one bank while reading from another. This is why DDR5's higher absolute latency in nanoseconds (slightly worse than DDR4) is offset by improved throughput — more banks mean more parallelism, hiding the precharge/activate overhead.

Real-world impact: Database engines like Redis and game engines carefully align hot data structures to exploit row buffer locality. When profiling shows high memory latency, the bottleneck is often row buffer conflicts, not raw bandwidth. Tools like Intel VTune report "DRAM bound" stalls broken down by cause — and row conflicts are frequently the culprit on multi-threaded workloads where threads thrash the same banks.