When a digital output switches, it doesn't pull current from some perfect, infinite voltage source. It pulls current through a real wire — package pin, bond wire, PCB trace — and that wire has inductance. Inductors resist sudden changes in current with a voltage: V = L · di/dt. The result is that the chip's internal "ground" momentarily rises above board ground, and its internal "VDD" momentarily sags below the supply. This is ground bounce (sometimes called simultaneous switching noise, SSN).

The mechanism: imagine 32 output drivers on a bus all switching from high to low at once. Each driver dumps charge from its load capacitance into the chip's ground network, which then has to push that current out through the ground bond wire to the board. If each driver sinks 20 mA and they all switch within 1 ns, that's 640 mA changing in 1 ns flowing through maybe 2 nH of bond wire inductance.

The calculation: V = L · di/dt = 2 nH · (0.64 A / 1 ns) = 1.28 V. The chip's internal ground just jumped 1.28 V above board ground. Any input that was a logic LOW (say 0.3 V relative to board) now looks like 0.3 - 1.28 = -0.98 V relative to chip ground — or, worse, a quiet output still being driven LOW might appear as a HIGH glitch to downstream logic. This is how "I didn't touch that pin" outputs spontaneously go wrong.

Real-world example: Early '90s SRAM chips with 8 wide outputs were notorious for ground-bounce-induced read failures when all 8 bits transitioned 0xFF→0x00. The fix was both physical and architectural: add more VSS pins (more parallel bond wires reduces effective L), stagger output switching by tens of picoseconds, and slew-rate-control the output drivers so di/dt is bounded.

Mitigation strategies:

• Multiple power/ground pins — two parallel 2 nH wires give 1 nH effective inductance. Modern BGA packages dedicate 30–50% of pins to power/ground for this reason.
• Decoupling capacitors placed within millimeters of the package supply the transient charge locally, so the bond wire only sees the average current.
• Controlled-slew output drivers trade edge rate for quiet switching — useful when timing margin allows.
• Output staggering — DDR memory controllers deliberately skew DQ transitions by ~50 ps to spread di/dt.

Rule of thumb: Budget ~1 nH per package pin and ~1 nH per cm of PCB trace. If your di/dt times that inductance exceeds ~10% of VDD, expect functional failures — not just noise on a scope, but bits flipping in latches.