Hamming codes can correct a single bit-flip per word. That's fine for DDR4 DRAM, where cosmic-ray-induced soft errors are rare and mostly isolated. But when you go to NAND flash, MLC/TLC cells, or radiation-hardened space electronics, you routinely see multiple bit errors per codeword. A single-bit-corrector will miscorrect these — it'll happily "fix" the wrong bit and hand you corrupt data with a green checkmark. This is where BCH codes (Bose–Chaudhuri–Hocquenghem, 1959–60) take over.

BCH is a generalization of Hamming built on Galois field arithmetic. The trick: pick a primitive element α in GF(2^m), and design a generator polynomial whose roots are α, α², α³, ..., α^(2t). Any codeword must be divisible by this polynomial. To correct t errors, you need 2t roots — which costs roughly m·t parity bits for a codeword up to 2^m − 1 bits long.

Rule of thumb: For a NAND flash page of 2048 bytes (16384 bits) correcting 8 errors with m=14: parity ≈ 14 × 8 = 112 bits. Correcting 40 errors in modern TLC flash: 14 × 40 = 560 bits of overhead per 1KB sector — about 7% overhead for the ECC.

The decode pipeline in hardware has three stages:

• Syndrome computation: plug α, α², ..., α^(2t) into the received polynomial. If all syndromes are zero, no errors. This is 2t parallel GF multipliers — cheap and pipelined.
• Berlekamp–Massey algorithm: from the syndromes, compute the error locator polynomial Λ(x) whose roots point at the flipped bit positions. This is the hardest block — it's an iterative feedback loop of GF multiply-accumulates, typically 2t cycles.
• Chien search: substitute every possible position (α^0, α^1, ...) into Λ(x). Wherever it evaluates to zero, that bit is flipped. This is embarrassingly parallel — high-end SSD controllers unroll it to check 32 or 64 positions per cycle.

Real-world example: Every modern NAND flash controller (Samsung, Micron, Marvell) runs BCH or its more powerful cousin LDPC. A typical enterprise SSD's BCH engine corrects 60+ bits per 1KB sector at throughputs above 10 GB/s. Without it, TLC/QLC NAND with raw bit error rates of 10⁻³ would be unusable — BCH drops the uncorrectable rate below 10⁻¹⁵.

The catch: latency scales with t. Correcting 40 errors takes ~80 cycles in Berlekamp–Massey alone. That's why controllers pipeline aggressively and why reads that hit the ECC's correction limit are 3–5× slower than clean reads.