Dynamic logic evaluates in two phases: precharge pulls an internal node high through a PMOS, then evaluate conditionally discharges it through an NMOS pull-down network. The output is only valid during evaluate. The problem: you cannot directly cascade dynamic gates, because during precharge every node is high — so a downstream NMOS network sees a "1" input and wrongly discharges its own precharged node before the upstream gate has actually computed anything.

Domino logic fixes this with one trick: put a static CMOS inverter after every dynamic gate. Now during precharge, the dynamic node is high, but the inverter output is low. Downstream NMOS transistors see 0 and stay off. When evaluate begins, dynamic nodes selectively fall, and their inverter outputs selectively rise — the "1"s ripple forward like dominoes tipping, one stage at a time. Each stage can only transition low-to-high, never the reverse, which is why it works without hazards.

Why anyone bothers: a domino NAND8 uses 9 transistors (8 NMOS + 1 PMOS + inverter) versus 16 for static CMOS, and the NMOS-only pull-down is roughly 2× faster because you never fight PMOS. Intel used domino aggressively in the Pentium 4's fast ALU, which ran at 2× the core clock — the entire 32-bit add-and-latch happened in a half-cycle by leaning on chained domino stages with no static logic in the critical path.

The catch — inversions: because every stage ends in an inverter, domino chains can only implement non-inverting functions natively (AND, OR, majority). Anything requiring an inverting stage forces you to duplicate the logic in complementary form (dual-rail domino) or break the chain with a static inverter and re-precharge, killing the speed advantage. This is why domino shows up in adders and comparators but rarely in general random logic.

Rule of thumb: A domino chain of N stages needs the evaluate window to satisfy t_eval ≥ N × (t_pd_dynamic + t_pd_inv). If your clock is 1 GHz with a 500 ps evaluate phase and each stage is ~40 ps, you can chain roughly 12 domino stages before the phase runs out. Beat that, and the last stages evaluate into precharge — corrupting the output.

Reliability cost: the dynamic node is high-impedance during evaluate. Leakage, charge sharing, and noise can drift it low even when no pull-down path fires, so every real domino gate needs a small keeper PMOS — a weak transistor holding the node high, fighting only leakage, not the evaluation network.