When a load misses L1 and the cache controller fetches a 64-byte line from L2, L3, or DRAM, those 64 bytes don't materialize at once. The memory bus is typically 32 bytes wide on modern chips, and DRAM bursts deliver chunks sequentially. The line arrives in beats — usually 2 beats from L2/L3 and 4–8 beats from DRAM depending on the burst length.

This creates two distinct latencies the rest of the pipeline cares about:

• Critical word latency: time until the specific 8 bytes the load actually wants are available for forwarding to the register file.
• Line fill latency: time until all 64 bytes have landed in the cache and the fill buffer can be retired.

The CPU optimizes for critical word latency with two tricks. Critical word first asks the memory controller to deliver the requested word in the first beat — DDR4/DDR5 support this via the burst-chop and column-address sequencing. Early restart wakes the dependent load the instant the critical word lands in the fill buffer, without waiting for the rest of the line. The load's consumers in the scheduler get woken up, the bypass network forwards the value, and execution continues. Meanwhile, the remaining beats trickle in over the next several cycles and the fill buffer eventually retires into the data array.

Concrete example: an Intel Skylake L2 hit is typically quoted at 12 cycles. That's critical word latency — what perf sees and what the scheduler plans around. But the fill buffer holds the line for roughly 16–18 cycles total before the data array is written and the MSHR releases. If a second load to the same line arrives during that gap, it hits the fill buffer (fast) rather than the data array (not yet populated).

Rule of thumb: critical word latency is what your dependent instruction chain sees; line fill latency is what the cache's bandwidth ceiling sees. For a 64-byte line on a 32-byte bus, line fill = critical word + 1 beat (~1 cycle for L2, 4–8 cycles for DRAM). If your workload is latency-bound on pointer chases, only critical word matters. If you're streaming and saturating the fill buffer pool (typically 10–12 MSHRs), line fill latency is what throttles you.

This is also why aligned loads matter beyond just avoiding split-line penalties: an aligned load's critical word is the first beat, so early restart fires immediately. A misaligned load straddling two lines may wait for the second line's critical word — doubling effective latency.