Cache Replacement Policies: How Hardware Decides Which Line to Evict When the Cache Is Full

2026-06-16

When a cache miss arrives and the target set is full, hardware has microseconds — actually picoseconds — to pick a victim. The replacement policy is the algorithm that makes that choice, and it's implemented entirely in gates because software is far too slow to be in the loop.

The candidates:

Concrete example: Intel's Skylake L3 is 16-way associative. True LRU would need 44 bits per set across millions of sets. Skylake uses a quad-age RRIP variant that needs only 32 bits per set and beats LRU on database and streaming workloads where LRU gets thrashed by large working sets.

Rule of thumb for hardware area: True LRU costs roughly N·log2(N) bits per set; Tree-PLRU costs N-1 bits; NRU and RRIP cost 1-2 bits per line. For anything beyond 4-way, designers almost never pick true LRU — the timing path through the age-comparison logic blows the clock budget.

The scan problem: LRU fails catastrophically on workloads that touch a working set larger than the cache once. Every line gets evicted right before it would be reused. RRIP fixes this by inserting new lines as "probably won't be reused," letting the existing hot lines survive a scan.

See it in action: Check out The CPU Cache - Short Animated Overview by BitLemon to see this theory applied.
Key Takeaway: True LRU is too expensive past 4 ways, so real caches use Tree-PLRU, RRIP, or even random — and on scan-heavy workloads the "dumber" policies often beat the textbook one.

All newsletters