2026-05-16
A PCB trace isn't a wire — it's a transmission line. When a fast edge travels down it and hits an impedance mismatch (like the high-impedance input of a CMOS gate), part of the energy reflects back toward the source. That reflection bounces off the driver, returns, and superimposes on the original signal. The result: ringing, overshoot, undershoot, and false triggering on the receiver.
The rule of thumb: if your trace's electrical length exceeds 1/6 of the signal's rise time, you need termination. At a 1 ns rise time and ~6 in/ns propagation speed on FR-4, that's about 1 inch. Anything longer, and reflections will appear inside the edge itself.
The four common termination schemes:
Real example — DDR4 fly-by topology: The clock and command lines daisy-chain across all DRAM chips and terminate at the far end through an on-die termination (ODT) resistor inside the last DIMM, programmable to 34Ω, 40Ω, 48Ω, etc. The memory controller picks the value based on signal integrity simulation of that specific board. The data lines, by contrast, use point-to-point with ODT enabled only on the receiver during reads.
Quick calculation: A 50Ω line driven into an open receiver has a reflection coefficient of (Z_L − Z₀)/(Z_L + Z₀) = (∞ − 50)/(∞ + 50) = +1. So 100% of the wave reflects back — a 3.3V edge becomes a 6.6V spike at the receiver before the energy dissipates. That's why unterminated CMOS often violates absolute maximum input voltage and slowly damages the pad's ESD diodes.
Modern SerDes lanes use on-die termination exclusively because stub lengths from a discrete resistor to the pad would themselves cause reflections at multi-Gbps rates.
