Dynamic logic precharges a node to VDD during the precharge phase, then evaluates by selectively discharging through an NMOS pull-down network. The output is supposed to stay high unless the inputs say otherwise. But there's a sneaky failure mode: charge-sharing. When the pull-down stack has internal nodes with their own parasitic capacitance, those nodes can steal charge from the output node even when the path to ground is broken — corrupting your "high" output into something ambiguous.

Picture a 4-input dynamic NAND: the output node sits on top of four stacked NMOS transistors (A, B, C, D) leading to ground. During precharge, the output goes to VDD, but the internal nodes between the stacked transistors might be at 0V (left over from a prior evaluation). Now suppose during evaluate, A=1, B=1, C=1, but D=0. There's no DC path to ground, so the output should stay high. But — when A, B, C turn on, the previously-precharged output node (capacitance C_out) suddenly shares its charge with the three internal nodes (capacitance C_int each), all initially at 0V.

The math: Charge conservation gives you the final voltage:

• V_final = VDD × C_out / (C_out + 3·C_int)
• If C_out = 30 fF and C_int = 5 fF each, V_final = VDD × 30/45 = 0.67·VDD
• That's well below the next stage's switching threshold — your "1" just became a "0"

Real-world example: The Intel Pentium 4's high-speed dynamic logic blocks had to be exhaustively analyzed for charge-sharing failures. Designers used SPICE to simulate every input pattern that could leave internal nodes low before evaluation, and inserted "keeper" PMOS transistors (weak pull-ups on the output) plus precharge devices on internal nodes — small PMOS transistors that precharge the stack's interior nodes alongside the output, so there's nothing for the output to share charge with.

Rule of thumb: If your pull-down stack is deeper than 3 transistors, you almost certainly need internal node precharge. A quick check: sum the internal parasitic capacitances and require C_out ≥ 10·ΣC_int to keep the worst-case droop under 10% of VDD. Anything less, and you're gambling that the bad input pattern never shows up — which in a billion-gate chip, it absolutely will.

Charge-sharing is why dynamic logic, despite being faster than static CMOS, is a niche technique used only where designers can afford full-custom layout and exhaustive electrical verification.