Every synchronous element in a CPU — every flip-flop, latch, and pipeline register — needs a clock edge to advance. On a modern die with billions of transistors, the clock has to arrive at all of them within picoseconds of each other, or the chip's timing assumptions collapse. This is the clock distribution problem, and solving it eats 20-40% of a CPU's total power budget.

The fundamental enemy: skew. If the clock reaches flip-flop A before flip-flop B, data launched from A might arrive at B before B has latched its previous value, causing a hold violation. If it arrives too late, you get a setup violation. At 5 GHz, your clock period is 200 ps. Industrial designs target less than 10 ps of skew across the entire die — roughly 5% of the cycle.

The H-tree. The classic solution: route the clock as a recursively branching H-shape. Each branch splits the path into two equal-length wires, so every leaf is electrically the same distance from the root. Buffer (repeater) chains amplify the signal at each level because wire RC delay grows quadratically with length. A modern desktop CPU might have 5-7 levels of H-tree, hundreds of thousands of clock buffers, and a clock spine shielded by dedicated power planes.

The mesh. H-trees alone aren't enough for billion-transistor chips. Intel and AMD high-performance designs add a top-level clock mesh — a grid of metal that shorts together many tree leaves. Mesh shorting averages out skew at the cost of more power (you're driving a giant capacitive grid). The Pentium 4 famously used a mesh; modern Zen and Core designs use hybrid tree+mesh.

Real example: AMD's Zen 4 CCD (core complex die) runs at up to 5.7 GHz. Each CCX has its own PLL that locks to a reference clock, then distributes via H-tree to a per-core mesh. Clock gating — disabling the clock to idle blocks — turns off roughly 90% of the tree's switching activity at any given moment, which is why your CPU isn't a 500W space heater.

Rule of thumb: Clock power scales as P = α × C × V² × f. For a 1 nF clock load at 1 V and 5 GHz with α=1 (clocks toggle every cycle), that's 5 W just for clock distribution. Halve the voltage and you quarter the power — which is why DVFS pays off so dramatically.

Modern twist: multi-domain clocking. Different blocks (cores, L3, memory controller, fabric) run at independent frequencies, with asynchronous FIFOs at the boundaries. This avoids forcing the whole chip to the worst-case timing path.