Once you strip the clock out of a design (Muller C-elements, QDI logic), you need a way for a sender and receiver to agree that data has been passed. That agreement is the handshake, and there are exactly two shapes it takes: 4-phase (return-to-zero, RZ) and 2-phase (non-return-to-zero, NRZ / transition signaling). The choice ripples through every latch, every wire, and every joules-per-op number in the design.

4-phase (RZ): Two wires — req and ack — that both idle low. A transaction is four events:

1. Sender drives req high (data valid)
2. Receiver captures, drives ack high
3. Sender drops req low
4. Receiver drops ack low — back to idle

Simple to build: a C-element and an inverter give you a full controller. The catch is that every transaction costs four wire transitions, and the "return-to-zero" half does no useful work — it just resets the protocol.

2-phase (NRZ): The edge itself is the event. Any transition on req (low→high or high→low) means "new data valid." Receiver responds with a transition on ack. Two events per transaction, half the switching energy, half the wire traffic. But your latch controller now needs to detect either edge, which typically means a Muller C-element wrapped with XORs — more transistors, harder layout, worse metastability behavior at the boundary.

Real-world example — IBM's async S/390 experiments and the ARM AMULET processors: AMULET1 used 2-phase because Sutherland's original micropipelines paper (1989) evangelized it. AMULET2 switched to 4-phase because the 2-phase latch controllers were larger, slower, and burned more static power than the simpler RZ controllers, despite doing half the wire transitions. That reversal became conventional wisdom: on-chip async almost always uses 4-phase; 2-phase survives off-chip where wire capacitance dominates.

Rule of thumb — when does 2-phase win? Energy per transaction is roughly:

• 4-phase: 4·C_wire·V² + 2·E_ctrl
• 2-phase: 2·C_wire·V² + 2·E_ctrl,2ph

where E_ctrl,2ph ≈ 2·E_ctrl because of the edge-detect logic. Solve for equality: 2-phase wins when C_wire·V² > E_ctrl — i.e., when the wire dominates. On-die at 1 mm, wire cap is ~200 fF and control cap is bigger; 4-phase wins. Off-chip at 10 cm on FR4, wire cap is ~10 pF and 2-phase wins by a wide margin.