You already know setup time and clock skew separately. Today: how engineers actually allocate the clock period into named budget lines and defend each one at signoff. Miss a slice and the chip fails at speed sort.

The equation everyone lives by. For a launch-to-capture path between two flip-flops on the same clock:

T_clk ≥ T_cq + T_logic + T_setup + T_skew + T_jitter + T_margin

Every term is a budget line. The synthesis tool doesn't invent time — it just spends whatever you gave it. If you don't reserve a slice for jitter, the tool happily uses it for logic, and silicon fails when the PLL wobbles.

A concrete split at 2 GHz (500 ps period), 7nm SoC.

• T_cq (clock-to-Q): 30 ps — the launching flop's output delay.
• T_setup: 25 ps — capture flop's requirement.
• Clock skew: 40 ps — H-tree imbalance after CTS.
• Clock jitter: 30 ps peak-to-peak — PLL + supply noise.
• OCV (on-chip variation) derate: 25 ps — statistical device mismatch.
• Margin (uncertainty): 50 ps — the engineer's paranoia buffer.
• Logic budget: 500 − 200 = 300 ps for actual combinational work.

So at 2 GHz you get 300 ps for logic — roughly 15 gate delays in that node. Push clock to 3 GHz (333 ps period) and the fixed overhead (200 ps) barely shrinks; logic budget collapses to 133 ps. That's why frequency scaling flattens: the overhead is nearly constant, not proportional.

Rule of thumb: in modern nodes, reserve ~40% of your clock period for non-logic overhead (skew + jitter + setup + Tcq + margin). If your tool reports the logic path is meeting timing at 90% of T_clk, you're lying to yourself about jitter and OCV.

Real-world example: Intel's Pentium 4 pushed to 3.8 GHz (263 ps period). The Prescott revision had a stage where the overhead consumed ~170 ps, leaving ~90 ps for logic — about 3–4 gates. That's why some pipeline stages had almost no logic in them and were essentially just wire and flop. It's also why the P4 died: adding one more gate to any critical stage broke everything.

The debugging move: when a chip fails at speed but passes STA, someone stole from the margin budget. Common thieves: unbudgeted supply droop under workload, IR drop on the clock buffer rail, or a CTS engineer who "optimized" skew from 40 ps to 20 ps by shrinking buffers that then couldn't drive their loads at hot corner.