A ripple-carry adder is beautifully small — one full-adder per bit, wired head-to-tail — and horribly slow, because the carry has to physically walk through every stage. A Kogge-Stone tree fixes the speed but explodes the transistor count and wire congestion. The carry-skip adder (also called carry-bypass) is the pragmatic middle path: keep the ripple chain, but let the carry jump over whole blocks when it's obvious the block will just pass it through.

The trick lives in one Boolean observation. A full-adder stage generates its own carry when both operand bits are 1 (generate, G = A·B) and propagates an incoming carry when exactly one is 1 (propagate, P = A⊕B). For an N-bit block, the block propagate BP = P₀·P₁·…·P_{N-1}. When BP=1, every bit in the block is in "pass-through" mode, and the block's carry-out equals its carry-in — no waiting required.

The hardware adds one AND gate for BP and one 2:1 mux at the block's carry-out. If BP=1, the mux selects the carry-in directly. If BP=0, it selects the actual rippled carry-out from the last full-adder in the block. The carry either ripples through the block (slow path) or skips over it (fast path) — whichever wins in that particular addition.

Sizing the blocks matters more than the concept. Equal-sized blocks are suboptimal. The worst case is a carry that ripples through the first block, skips several middle blocks, then ripples through the last block. Ripple delay is linear in block size; skip delay is constant. So the optimal design uses variable-length blocks — small at the ends, larger in the middle. The classic rule of thumb for an N-bit adder: block sizes grow then shrink, with the middle block of size ~√(N/2). For a 32-bit adder, a common variable-block partition is [2,3,4,5,5,4,3,2,4] — 32 bits total, worst-case delay ~2√N gate delays instead of ripple's N.

Real-world example: Carry-skip adders show up in low-power microcontrollers and DSP address generators where full lookahead is overkill but you can't tolerate a 32-cycle ripple. The ARM Cortex-M0's ALU uses a hybrid with skip-style bypass on the upper bits — cheaper than Kogge-Stone, fast enough at 50 MHz, and drops the transistor count by ~30% versus a full parallel-prefix design. That's a real power win on a battery-powered part.

Quick calc: A 16-bit ripple adder at 50 ps/stage takes ~800 ps. A 16-bit carry-skip with four 4-bit blocks: 4 stages ripple + 3 skip muxes + 4 stages ripple ≈ (4+3+4)×50 = 550 ps. A 30% cut for one AND gate and one mux per block.