This repository is a genuine hidden gem for anyone curious about computer architecture from the ground up. It contains two complete SystemVerilog implementations of a 32-bit RISC-V (RV32I) processor core — a great pairing for learning, because you get to see the same instruction set architecture realized at two very different levels of complexity.

The two implementations are:

• A single-cycle core — the textbook starting point, where every instruction completes in one clock cycle. Simple to read, simple to reason about, and a perfect introduction to how fetch/decode/execute/memory/writeback fit together.
• A 5-stage pipelined core — the more realistic design, complete with hazard resolution. This is where things get interesting: forwarding paths, stall logic, and branch handling are the bread and butter of real CPU design, and seeing them implemented in a small, readable codebase is far more instructive than reading about them in a textbook.

What makes this repo stand out from the many half-finished RISC-V cores on GitHub is the pedagogical pairing. Most student projects ship one design and call it done. Having both side by side lets you diff the architectures and really internalize why pipelining matters and what it costs in complexity.

Who would benefit?

• CS/EE students taking a computer architecture course who want a reference implementation to compare against their own labs.
• FPGA hobbyists looking for a clean, hackable soft-core to drop onto a Lattice or Xilinx board.
• Self-taught engineers trying to bridge the gap between Patterson & Hennessy and actual HDL.
• Anyone preparing for hardware interviews where pipeline hazards inevitably come up.

RISC-V's open ISA is what makes projects like this possible — and this one deserves more than zero stars.