You have two clocks — say a 100 MHz fast clock for active mode and a 32 kHz slow clock for sleep — and a select bit that picks one. The naive solution is a 2:1 mux. The naive solution is wrong, and it will eat your chip alive.

Consider what happens when sel flips from 0 to 1 in the middle of a clock-A high pulse, while clock-B happens to be low. The mux output drops instantly to 0, then rises when B rises. You just created a runt pulse — a high period shorter than either source clock. Downstream flip-flops see this as a clock edge, but the pulse width violates their minimum pulse-width spec. Result: metastability, undefined state, sometimes a hung core that requires a power cycle.

The standard fix is the glitch-free clock mux, built from two cross-coupled enable paths, each clocked by the opposite clock's falling edge:

• Each clock has an enable flop, clocked on its own falling edge.
• Each enable can only assert when the other clock's enable is deasserted (cross-coupled AND with the inverted partner).
• The selected clock is ANDed with its enable, then ORed together at the output.

The key insight: a clock is only gated on or off when it is already low. Using the falling edge to register the enable guarantees the AND gate's input is 0 when the enable changes. No matter how chaotic sel is, the output transitions cleanly between full pulses of A and full pulses of B, with a guaranteed dead time of at least half a slow-clock period in between.

Concrete example: Every smartphone SoC does this. When Android tells the CPU cluster to drop from 2 GHz to a 24 MHz sleep clock, a glitch-free mux performs the handoff. If it weren't glitch-free, every screen-off transition would risk crashing the AP.

Rule of thumb for switching latency: the handoff costs roughly 1 cycle of the outgoing clock + 1 cycle of the incoming clock, because each side needs a falling edge to update its enable. Switching from 100 MHz to 32 kHz takes ~31 µs — dominated entirely by waiting for the slow clock's falling edge. Software that toggles clocks every few microseconds will spend most of its time stuck mid-handoff.

One gotcha: if either source clock stops while selected, you can never switch away — there's no falling edge to clear the enable. Real designs add a force-off override and sometimes a third "safe" always-on reference clock for this exact failure mode.