Domino logic chains dynamic gates together — each stage precharges its output node high during the precharge phase, then conditionally discharges through an NMOS pull-down network during evaluate. The classic structure has a footer transistor: an NMOS device in series with the pull-down network, gated by the clock. The footer's job is simple — it blocks the discharge path during precharge so the precharged node doesn't accidentally drain through the logic while the PMOS is also trying to pull it high. Footless domino removes that transistor.

Why remove it? The footer is in series with every input pattern, so it adds ~15-25% to evaluation delay on a typical 4-input NAND domino gate. In a deeply pipelined high-frequency datapath — think the integer ALU of a 5 GHz CPU — that's a critical-path tax you'd rather not pay. Footless domino drops the transistor, leaving the pull-down network connected directly to ground. Evaluate gets faster; layout shrinks.

The cost is real. Without the footer, the pull-down network is always connected to ground. During the precharge phase, if any input is high, the PMOS precharge transistor and the NMOS pull-down network fight each other — a brief contention current flows from VDD to GND. This wastes power and, more importantly, can leave the precharge node at a degraded voltage (maybe 0.8·VDD instead of full VDD). The next stage's noise margin shrinks. Worse: if inputs aren't monotonically rising during evaluate (the cardinal rule of domino), a footless gate can be discharged spuriously during precharge and never recover.

The rule of inputs: footless domino only works when its inputs come from the outputs of other domino gates in the same clock phase. Those outputs are guaranteed low during precharge (they were either discharged or untouched from the prior cycle's reset), so no contention occurs. The first stage of a domino chain — the one fed by static logic or flip-flops — must be footed, because static inputs can be high during precharge.

Real-world example: Intel's Pentium 4 used footless domino aggressively in its double-pumped integer ALU running at 2× the core clock. The first gate after each latch was footed (interfacing with static signals); internal gates in the cascade were footless to hit timing.

Rule of thumb: footer adds ~3 inverter-delays of delay and ~2% area; footless saves both but requires the previous stage to be domino. In a 6-stage domino cascade, footing only stage 1 saves you ~12% of the chain's delay versus footing everything.