The Reorder Buffer (ROB) has two knobs: width (how many instructions it can dispatch, issue, and retire per cycle) and depth (how many in-flight instructions it can hold). Both look like free performance — bigger numbers mean more parallelism. They aren't. They trade against each other in ways that explain why ROBs have grown so slowly compared to transistor budgets.

Width costs quadratically. A 4-wide machine needs every dispatched instruction to check 4 sources against 4 destinations for dependencies. An 8-wide machine doesn't just double that — it quadruples the rename comparator count, doubles the register file write ports, and demands a select tree that finds 8 ready instructions out of the issue queue every cycle. Apple's M-series cores went 8-wide at decode; Intel and AMD stayed at 4–6 for a decade because the wire delay across a wider rename stage threatened the clock frequency.

Depth costs energy and squash penalties. A deeper ROB lets the CPU look further past a cache miss, exposing more memory-level parallelism. But every entry stores a uop, its rename info, exception state, and PC. Skylake's 224-entry ROB holds roughly 28 KB of state when you count all the side tables. Worse, on a branch misprediction, every speculative instruction in that 224-entry window gets squashed — and the deeper the ROB, the more wasted work per misprediction.

The rule of thumb: ROB depth should roughly equal issue width × average memory latency in cycles. With a 300-cycle DRAM miss and a desire to keep 4 misses in flight on a 6-wide machine, you'd want around 6 × 300 / (instructions-per-miss) ≈ 200–300 entries. Going deeper than that hits the MLP wall: you can't find more independent loads anyway.

Concrete example: Intel's Golden Cove (Alder Lake P-core, 2021) jumped ROB from 352 to 512 entries while only widening dispatch from 5 to 6. They bet on depth because the memory wall got worse faster than the parallel-decode problem got easier. Apple's Firestorm did the opposite — 8-wide decode with a "only" ~630-entry ROB — because their lower-latency memory subsystem made width pay off more than depth.

The wires tell the story: wider machines need short wires between many units, while deeper machines need fewer but longer wires to track distant in-flight work. Modern designs split the difference by clustering execution units, which lets width grow without every wire crossing the whole die.