Every SAR ADC you've seen hides a DAC inside it, and 90% of the time that DAC is a charge redistribution array — a bank of binary-weighted capacitors that produces an analog voltage by rearranging charge, not by burning current through resistors. This is why modern CMOS ADCs are so power-efficient: capacitors don't dissipate DC power the way an R-2R ladder does.

The core idea. You build N capacitors with values C, C/2, C/4, ..., C/2^(N-1), plus one dummy C/2^(N-1) to make the total sum a clean power of two. Each capacitor's bottom plate connects through a switch to either V_ref or GND. The top plates all tie together to form the DAC output node.

Three-phase operation:

• Sample: Top plate shorted to a bias (often GND via a switch), all bottom plates connect to V_in. Each cap stores charge proportional to V_in × its own capacitance.
• Hold: Top plate switch opens, trapping the total charge Q = C_total × V_in on the floating node.
• Redistribute: Bottom plates switch to V_ref or GND based on the digital code. Charge conservation forces the top plate to a new voltage: V_out = -V_in + (D/2^N) × V_ref, where D is the digital code. Feed this into a comparator and you've built the guts of a SAR ADC.

Real-world example: The Analog Devices AD7091R (12-bit, 1 MSPS SAR ADC) uses exactly this topology. It draws only 350 µA at full speed because the capacitor array only burns dynamic switching energy — no static current path from V_ref to GND. Compare that to an R-2R ladder DAC of the same resolution, which would sink milliamps continuously through the resistor network.

Rule of thumb — matching sets your ENOB. Capacitor mismatch in a standard CMOS process is roughly σ(ΔC/C) ≈ A_C / √(W×L), where A_C ≈ 1%·µm for metal-metal caps. To hit 12-bit linearity (0.024% matching, 3σ), you need unit caps around (3 × 1% / 0.024%)² ≈ 15,000 µm² — that's a 122µm × 122µm capacitor as your LSB unit. Push to 14 bits and the area quadruples. This is why split-array architectures exist: put a coupling cap between an MSB sub-array and an LSB sub-array so you don't need a 2^N ratio in one monolithic bank.

The gotcha: Parasitic capacitance on the top plate — from the comparator input, the switch itself, and routing — attenuates the output. If C_parasitic = 0.1 × C_total, you lose ~10% of your signal swing and every step gets smaller. Layout matters more here than in almost any other analog block.