Every CMOS gate you've ever drawn has been balanced: the PMOS pull-up network and NMOS pull-down network are sized so the gate switches at roughly Vdd/2, giving symmetric rise and fall times. But sometimes you don't care about both edges equally — you care about one direction being fast. That's where skewed CMOS comes in.

A skewed gate deliberately upsizes one network and downsizes the other, shifting the switching threshold and making one transition faster at the expense of the other. Two flavors:

• HI-skew (P-skew): Oversized PMOS, undersized NMOS. Switching threshold rises above Vdd/2. Rising output edge is fast; falling edge is slow.
• LO-skew (N-skew): Oversized NMOS, undersized PMOS. Threshold drops below Vdd/2. Falling edge fast; rising edge slow.

Why deliberately make a gate worse in one direction? Because in domino logic chains, only the evaluation edge matters. The precharge phase just resets nodes to Vdd — nobody is racing during precharge. So you build the inverters between dynamic stages as HI-skew gates: they propagate the rising "evaluate" edge fast, and the slow falling edge happens harmlessly during the next precharge cycle.

Real-world example: The Pentium 4's integer ALU ran at 2× the core clock (the famous "fast ALU" at 7 GHz effective in 2003). It used self-resetting domino logic where every stage was HI-skewed. By making PMOS roughly 3× the normal width and NMOS roughly half-width, Intel cut the critical rising-edge delay by ~30%, which was the difference between hitting frequency target and missing it. The falling edge took 2-3× longer, but that happened during precharge when nothing was waiting.

Rule of thumb for skew ratio: For a HI-skew inverter, size PMOS:NMOS at roughly 4:1 instead of the standard 2:1 (which already compensates for hole mobility being half of electron mobility). That shifts the switching threshold from ~Vdd/2 to about 0.6·Vdd, which speeds the rising edge by ~25% while slowing the falling edge by ~40%. For LO-skew, flip it: PMOS:NMOS at roughly 1:1, threshold drops to ~0.4·Vdd.

The catch: skewed gates have worse noise margins in one direction, draw more leakage (the oversized transistor is always partially conducting), and you can never use them in a normal static logic path because the slow edge will violate timing. They're a tool for specific domino contexts where you control both phases of the clock.