For thirty years, rep movsb was the instruction you told juniors never to use. It copied one byte per iteration through microcoded overhead, and any competent memcpy used SSE, then AVX, then AVX-512 with elaborate alignment prologues and epilogues. glibc's memcpy ballooned to over 1000 lines of hand-written assembly per microarchitecture.

Then Ice Lake (2019) shipped Fast Short REP MOV (FSRM), advertised via CPUID.(EAX=7,ECX=0):EDX[bit 4]. When set, the CPU implements rep movsb and rep stosb in hardware: the front-end recognizes the pattern, allocates internal buffers, and streams cache-line-sized transfers through the same wide datapath the vector unit uses. No microcode. No per-byte iteration.

The practical effect: glibc 2.35+ dispatches to a variant that is literally:

• mov rcx, rdx (length into count register)
• rep movsb (copy)
• ret

This beats the AVX-512 variant for sizes from ~128 bytes up to L2 cache size, because it has zero setup cost (no alignment check, no head/tail masking), doesn't trigger AVX-512 frequency downclock, and the CPU internally chooses the optimal transfer width based on alignment and length it can see in one shot.

Concrete example: On a Sapphire Rapids Xeon, copying 4KB pages with rep movsb hits ~48 GB/s per core. The old AVX-512 memcpy hits ~44 GB/s but drags the core's frequency down from 3.4 GHz to 2.6 GHz for ~2 ms afterward, which slows every unrelated instruction on that core. Netflix documented exactly this in 2022 when their video-transcode pipeline got slower after they "optimized" their copy loop with intrinsics.

Rule of thumb: If CPUID reports FSRM and your copy is between ~64 bytes and the L2 size (typically 1-2 MB), rep movsb is either the fastest option or within 5% of it — and it never causes downclocking. Below 64 bytes, an inline mov sequence wins because rep still has a ~15-cycle startup latency. Above L2, streaming stores (movntdq) win because they bypass the cache entirely.

There's a related bit: ERMS (Enhanced REP MOVSB, from Ivy Bridge) accelerated long copies. FSRM is the newer bit that finally made short ones fast — the "short" case is where hand-written vector code used to dominate. Both bits set means the CPU is fast at every length; check both before dispatching.

The lesson: the microarchitecture ate the library. Decades of hand-tuned memcpy assembly became a two-instruction fallback because the hardware moved the optimization inside the pipeline.