Successive Approximation ADCs: How Hardware Converts Analog with a Binary Search

2026-05-10

If sigma-delta ADCs trade speed for resolution by oversampling, the Successive Approximation Register (SAR) ADC takes the opposite approach: it converts one sample in N clock cycles for N bits of resolution, using a binary search. SAR ADCs dominate the 8–18 bit, 100 kSPS to 10 MSPS space — exactly where microcontrollers, industrial sensors, and battery monitors live.

The architecture has four pieces: a sample-and-hold capacitor, a comparator, a DAC, and the SAR logic. The conversion proceeds bit-by-bit from MSB to LSB:

In practice, the DAC is built from a charge-redistribution capacitor array — binary-weighted caps (C, 2C, 4C, ... 2N-1C) that share charge with the sampling cap. This means the same capacitors do double duty as the sample-and-hold and the DAC, which is why SARs are tiny and low-power.

Real-world example: The TI ADS8689 is a 16-bit, 100 kSPS SAR used in industrial data acquisition. It draws 15 mW and clocks its internal SAR at ~2 MHz to deliver 16 conversions in 16 cycles + sample time. Compare to the STM32's built-in 12-bit SAR, which can hit 5 MSPS at 12 bits — every smart thermostat, motor controller, and oscilloscope front-end has one.

Rule of thumb: SAR conversion time = (N + 1.5) × Tclk. For 12 bits at 20 MHz internal clock, you get ~675 ns per sample → ~1.5 MSPS. Double the clock, double the rate — until the comparator's settling time becomes the bottleneck (typically above 50 MHz).

The killer limitation is capacitor matching. To hit 16-bit linearity, the MSB cap must match the sum of all lower caps to 1 part in 65,536 — about 15 ppm. Trimming, calibration, or dithering is required above 12 bits. Below that, raw silicon matching is good enough, which is why every cheap MCU includes a 10–12 bit SAR for free.

See it in action: Check out Successive Approximation ADC Explained by ALL ABOUT ELECTRONICS to see this theory applied.
Key Takeaway: SAR ADCs do a binary search with a comparator and a switched-cap DAC, delivering N bits in N clocks — the workhorse converter for medium-speed, medium-resolution applications.

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