Normal pipelining inserts flip-flops between logic stages so each cycle holds exactly one "wave" of data. Wave-pipelining deletes those intermediate registers and instead launches a new input before the previous one has finished propagating — multiple data waves coexist in the same combinational cloud, separated only by their propagation delay. The clock period sets the wave spacing; the logic itself becomes the storage.

The trick relies on bounding the delay spread through the logic. Every path from input register to output register has some min delay d_min and max delay d_max. For N waves to coexist safely, you need:

• No collision (max delay constraint): d_max + t_setup < N·T_clk
• No overrun (min delay constraint): d_min − t_hold > (N−1)·T_clk

Subtract them and you get the killer inequality: d_max − d_min < T_clk − t_setup − t_hold. The spread between fastest and slowest path must fit inside one clock period minus flip-flop overhead. This is brutal — normal synthesis happily produces paths with 3:1 delay ratios. Wave-pipelining demands tight, balanced logic where every path takes nearly the same time.

Concrete example: a 64-bit carry-lookahead adder has d_max ≈ 2.0 ns and d_min ≈ 0.6 ns. Spread = 1.4 ns. With a 1 ns clock period and 0.15 ns setup+hold overhead, you'd need spread < 0.85 ns — fails. But pad the fast paths with buffers to raise d_min to 1.2 ns (spread = 0.8 ns) and you can run 2 waves in flight at 1 GHz, doubling throughput without adding a pipeline register. Cray's vector units and some 1990s DEC Alpha multipliers used this exact technique to hit clock targets without paying register-file area.

Rule of thumb: wave-pipelining is worth attempting only when register insertion is impossible (analog-style paths, ultra-low-latency loops) or when register power/area is the bottleneck. The design effort is roughly 5× a normal pipeline because you must actively slow down fast paths with delay buffers — and any process/voltage/temperature drift that widens the spread breaks the circuit.

Modern static timing tools barely support it. You typically need custom delay-matching scripts plus on-die delay-line trimming to compensate for PVT variation. That's why you see wave-pipelining in academic papers and a handful of GPU datapaths, but not in mainstream RTL — when registers cost almost nothing, paying 5× design effort to save them rarely pencils out.