A standard 6T SRAM cell has one word line and one bit-line pair. Assert the word line, and you get one access — read or write — per cycle. But video frame buffers, network packet queues, and CPU register files all need two independent clients touching the same memory at the same time. The producer writes while the consumer reads. Waiting your turn is not an option.

The answer is the dual-port SRAM cell, typically implemented as 8T: the original 6T storage core plus two extra access transistors and a second word line and bit-line pair. Port A and Port B each have their own address decoder, their own sense amplifier, their own word line, and their own bit lines. Both ports can be active in the same cycle — hitting different addresses — and neither one knows the other exists.

The two flavors:

• True dual-port (2R/2W): Both ports can read or write, independently. Full flexibility, biggest cell (~1.4× the area of single-port).
• Simple dual-port (1R/1W): Port A writes only, Port B reads only. Cheaper, and covers 90% of real use cases (FIFOs, frame buffers, streaming pipelines).

The collision problem: what if both ports address the same cell in the same cycle, and one is writing? The hardware has three choices, and you pick when you instantiate the block:

• Read-first: Port B returns the old value while Port A writes the new one. Safe, deterministic, but the reader sees stale data for one cycle.
• Write-first (transparent): Port B returns the new value being written. Zero read-write latency but requires the write data to be forwarded through combinational logic.
• Undefined: The output is X. Fastest cell, but your RTL must guarantee no collision — usually via address bookkeeping.

Real-world example: a CPU register file with two read ports and one write port (2R/1W) uses this exact structure. Every cycle, the pipeline decodes an instruction, reads rs1 and rs2 simultaneously through the two read ports, and writes back the previous cycle's result through the write port. Without dual-port SRAM, superscalar execution is impossible.

Rule of thumb: each additional port adds roughly 2 transistors per bit cell (one access transistor per side of the cross-coupled inverter pair). A 4-read/2-write register file cell is ~18T — three times the area of a plain SRAM cell, which is why register files are aggressively hand-designed and why you don't see 8-port SRAMs above a few kilobytes.