Every CMOS chip contains a hidden enemy built into its own structure: a parasitic SCR (silicon-controlled rectifier) formed by the NMOS and PMOS transistors sitting next to each other in the substrate. Under normal conditions, this SCR is dormant. Trigger it, and it creates a low-resistance short from VDD to GND that draws amps until the chip melts or the power supply trips. This is latch-up, and it's killed more chips than anyone wants to admit.

The parasitic structure. A CMOS inverter has a PMOS in an n-well and an NMOS in the p-substrate. The PMOS source (VDD) → n-well → p-substrate → NMOS source (GND) path forms a PNPN structure — two cross-coupled bipolar transistors (one PNP, one NPN). The base of each is the collector of the other. If either turns on, it feeds base current to the other, which feeds back more current. Positive feedback. Once triggered, the SCR latches on and only powering down breaks it.

What triggers it. Anything that injects enough current into the substrate or well to forward-bias a base-emitter junction by ~0.6V:

• I/O overshoot/undershoot: A pin driven above VDD or below GND injects current through the ESD diodes into the substrate.
• Power sequencing: If an I/O pin sees voltage before VDD ramps up, the parasitic diode forward-biases.
• Voltage transients on VDD/GND rails, ionizing radiation strikes, or hot-plug events.

How designers prevent it. The fix is geometry and doping, not logic:

• Guard rings: Heavily-doped substrate/well contacts surrounding sensitive transistors, soaking up stray carriers before they reach a base.
• Substrate/well taps placed every ~25µm minimum (foundry rule), keeping the parasitic resistance low so injected current can't build up enough voltage to bias the BJT.
• Triple-well processes isolating NMOS in their own p-well inside a deep n-well, breaking the PNPN path entirely.
• Epitaxial substrates (lightly-doped epi on heavily-doped bulk) which shunt substrate current away from active regions.

The rule of thumb: Latch-up immunity is specified by the JEDEC JESD78 standard — a chip must survive ±100mA of injected current at each I/O pin without latching. A real-world example: the Galileo spacecraft's RCA 1802 processor used silicon-on-sapphire (SOS) precisely because its dielectrically-isolated transistors had no shared substrate — eliminating latch-up entirely in Jupiter's radiation belts, where heavy ions would have triggered SCRs in bulk CMOS within minutes.

If you've ever seen a board where the chip gets blazing hot only after a glitchy power-on, and a power cycle "fixes" it — you've seen latch-up.