Every storage element we've covered so far — SRAM, DRAM, flip-flops, latches — forgets everything the moment you cut power. Flash remembers, but it's slow, wears out, and needs high voltages to program. MRAM (Magnetoresistive RAM) is the interesting middle ground: SRAM-like access speed, DRAM-like density, and non-volatility that survives years without power.

The storage element is a Magnetic Tunnel Junction (MTJ): two ferromagnetic layers separated by a ~1 nm insulating oxide barrier (usually MgO). The bottom layer's magnetization is pinned. The top layer's magnetization is free — it can point parallel (P) or antiparallel (AP) to the pinned layer. Electron spin tunneling through the oxide gives you two very different resistances:

• Parallel state (logic 0): low resistance, typically ~5 kΩ
• Antiparallel state (logic 1): high resistance, typically ~10 kΩ

The ratio (R_AP − R_P) / R_P is the Tunnel Magnetoresistance (TMR) ratio. Modern MTJs hit TMR of 150–200%, meaning the "1" state has 2–3× the resistance of the "0" state — plenty for a sense amp to distinguish.

Writing uses Spin-Transfer Torque (STT): push a current through the MTJ in one direction and the spin-polarized electrons flip the free layer to parallel; reverse the direction and it flips to antiparallel. Write currents are typically 20–100 µA for a few nanoseconds. Reading is easy — apply a small voltage (well below the write threshold), measure the current, compare to a reference.

Real-world example: Everspin ships standalone STT-MRAM chips used in enterprise SSD write caches. When the SSD loses power mid-write, the DRAM cache would normally lose everything — instead, the controller mirrors writes into MRAM, which retains data indefinitely without the supercap-and-flush dance that battery-backed DRAM needs. TSMC and Samsung now offer embedded MRAM as a replacement for embedded flash in microcontrollers at 22nm and below, because flash doesn't scale past 28nm cost-effectively.

Rule of thumb — retention vs write energy tradeoff: The energy barrier holding the free layer in place is E_b ≈ 40–60 kT for 10-year retention at 85°C. Retention time follows τ = τ₀ · exp(E_b / kT). Doubling the barrier doesn't double retention — it squares it. But higher barriers need proportionally more write current, so designers pick E_b just high enough for their application: 60 kT for storage-class memory, 30 kT for last-level cache where you refresh often.

The catch: read disturb. Every read pushes a small current through the MTJ, and if you read the same cell billions of times, thermal jitter plus that read current can occasionally flip it. Designers keep read current ≤ 1/10 of write current to push disturb error rates below 10⁻¹⁵.