In a healthy CMOS circuit, once inputs settle, no current flows. PMOS pulls high or NMOS pulls low — never both at once. The supply current in this idle state, called Iddq (Idd-quiescent), should be picoamps to nanoamps: just transistor leakage. If you measure microamps or milliamps instead, something is broken inside the die.

That's the whole insight behind Iddq testing. Apply a test vector, let the circuit settle, measure VDD current. A bridging defect — a metal whisker shorting two nets, a gate oxide pinhole, a via that didn't fully etch — creates a path from VDD to GND that conducts whenever the shorted nets are at opposite logic levels. The functional output might still look correct (the short pulls weakly, the driver wins), so traditional stuck-at testing misses it. But the current signature is unmistakable: orders of magnitude above baseline.

Why this matters for reliability: a bridging defect that passes functional test today often becomes a stuck-at failure six months later as electromigration widens the short. Iddq catches latent defects before they ship. In the 1990s, HP famously reduced field returns by 30× by adding Iddq screening to their ASIC flow.

The test flow:

• Generate vectors that toggle every internal node to both states (high coverage of possible bridges)
• For each vector, stop the clock, wait ~1ms for transients to die
• Measure IDD with a precision ammeter integrated into the tester's power supply
• Compare against threshold — typically 10× the leakage floor

The arithmetic that killed Iddq at advanced nodes: at 180nm, a chip might draw 1µA quiescent, and a defect shows up as 100µA — a 100× signal-to-noise ratio, trivial to detect. At 7nm, subthreshold leakage alone is hundreds of milliamps across billions of transistors. A defect adding 100µA disappears into the noise. Rule of thumb: Iddq stops being useful when leakage current exceeds ~100µA per million gates.

Modern variants try to rescue it. Delta-Iddq measures the change in current between vector pairs, canceling out the constant leakage. Iddq signatures use statistical outlier detection across many vectors per die — a defective chip's Iddq vector looks anomalous compared to its neighbors on the wafer, even if no single measurement crosses a threshold. Foundries at 5nm still run delta-Iddq on critical mixed-signal blocks where the leakage is lower.