DRAM stores each bit as a charge in a tiny capacitor, and those capacitors leak. If you don't periodically read and rewrite each row, the data evaporates within milliseconds. The fix — refresh — is one of DRAM's dirtiest secrets: your memory regularly stops answering the CPU so it can remind itself what it's holding.

The JEDEC standard requires every row to be refreshed within a retention time (tREFI window) of 64 ms at normal temperatures, or 32 ms above 85°C. A modern DDR4/DDR5 bank holds ~32K-128K rows. The memory controller issues a refresh command (REF) every tREFI = 7.8 µs (3.9 µs in hot mode), and each refresh takes tRFC — anywhere from 350 ns on small DDR4 chips to 880 ns on a 32Gb DDR5 die.

The overhead math: tRFC / tREFI = 880 ns / 7800 ns ≈ 11% of memory bandwidth literally vanishes on big DDR5 parts. On older 8Gb DDR4 it's closer to 3-4%. As capacities grow, refresh eats a larger slice — this is one reason DDR5 introduced same-bank refresh and fine-granularity refresh, letting the controller refresh one bank while others keep serving requests.

Real-world example: Rowhammer attacks exploit exactly this physics. By hammering a row thousands of times within the 64 ms refresh window, attackers induce charge leakage in adjacent rows fast enough to flip bits before the next refresh saves them. Modern DDR5 ships Refresh Management (RFM) and on-die Target Row Refresh (TRR): the chip counts row activations and sneaks in extra refreshes for victim neighbors. This costs bandwidth — your "11%" can climb to 15%+ under adversarial access patterns, and benchmarks like memtester show measurable slowdowns when TRR fires aggressively.

What it means for performance:

• Latency-sensitive workloads see random tail-latency spikes of ~500-900 ns whenever a request lands on a bank mid-refresh. Trading systems and real-time audio engineers chase these jitter sources for years.
• Server BIOS often exposes refresh rate multipliers (1x, 2x, 4x). Overclockers set 2x to skip every other refresh — works great until summer arrives and your machine corrupts memory above 85°C.
• Rule of thumb: refresh overhead ≈ tRFC / tREFI. If your DIMM datasheet lists tRFC=550ns, you're losing ~7% bandwidth to refresh before anyone touches the memory bus.

The cruel irony: DRAM density doubles, but tRFC scales roughly linearly with row count, so each generation pays more refresh tax than the last. ECC RAM, HBM, and persistent memory all dodge this differently — but commodity DDR remains stuck rewriting itself, forever.