We covered ADC fundamentals earlier, but glossed over architecture. The choice between Successive Approximation Register (SAR) and Delta-Sigma (ΔΣ) converters is the single biggest decision you'll make when speccing a data acquisition system. Pick wrong and you'll either burn money on bandwidth you don't need or watch your noise floor swallow the signal.

SAR converters work like a binary search. The internal DAC tests each bit from MSB down, comparing against the sample held on an input cap. An N-bit conversion takes N clock cycles. Throughputs range from 100 kSPS to 10 MSPS at 12–18 bits. Latency is one sample — what you sampled now appears in the result register a microsecond later. This makes SARs perfect for control loops and multiplexed channel scanning.

Delta-Sigma converters oversample wildly (often 256× to 4096× the output rate) using a 1-bit modulator, then digitally filter and decimate. The modulator pushes quantization noise out of the band of interest (noise shaping) and the decimation filter removes it. You get 20–32 bits of resolution, but with significant latency — the digital filter has a group delay of dozens to hundreds of samples. Output rates are typically 10 SPS to 100 kSPS.

Concrete example: You're building a load cell amplifier for a precision scale. The strain gauge output is maybe 20 mV full-scale, you need to resolve micrograms, and the weight settles in 500 ms. A 24-bit delta-sigma like the ADS1232 at 10 SPS gives you ~20 noise-free bits — about 20 nV/LSB referred to input. A SAR here would be useless: even a 16-bit SAR has 300 nV/LSB and would need a 60× PGA front-end that adds its own noise. Conversely, for a 3-phase motor controller sampling three current sensors at 50 kHz with tight loop timing, a SAR like the ADS8688 wins — the delta-sigma's filter latency would destabilize your control loop.

Rule of thumb for ENOB vs speed: Doubling the oversampling ratio in a first-order ΔΣ adds 1.5 bits of resolution. For higher-order modulators (3rd order is common), each 2× OSR adds 2.5 bits per order above first. So a 3rd-order modulator at 256× OSR gets you roughly 8 + 3×(log₂256 × 1) ≈ 20+ effective bits from a 1-bit core.

Watch the input impedance trap: SARs have switched-cap inputs that draw kickback current at each sample — drive them with a low-impedance op-amp buffer. Delta-sigmas with internal buffers (look for "buffered input" in the datasheet) tolerate megohm sources.