2026-05-28
Logic BIST tests random combinational paths, but memories need their own test discipline. A modern SoC has hundreds of SRAM instances totaling tens of megabits, and external testers can't poke every cell through a narrow JTAG pin — the test would take hours per chip. Memory BIST (MBIST) embeds a small controller next to each SRAM that walks every address with carefully crafted patterns, all running at functional clock speed.
The patterns aren't random. They're March algorithms — sequences of read/write operations applied in a strict address order (ascending ⇑ or descending ⇓). The classic March C- algorithm has six elements:
Total operations: 10N for N cells. A 1 Mbit SRAM at 1 GHz finishes in 10 ms. Compare that to a tester applying patterns through a 50 MHz JTAG: 200× slower.
Each March element catches specific fault models. Stuck-at faults (cell permanently 0 or 1) fall to any read. Transition faults (cell can hold a value but can't switch one direction) need a write-then-read pair — element 2 catches "can't go 0→1," element 3 catches "can't go 1→0." Coupling faults (writing cell A flips cell B) require both address directions: a fault where the aggressor sits at a lower address only shows up when you traverse upward, and vice versa. Address decoder faults (two addresses select the same cell) get caught when one cell's expected value disagrees with what's read.
Real-world example: ARM's Cortex-M7 cache RAMs ship with embedded MBIST controllers that run March C- at boot and report pass/fail through a status register. Automotive ISO 26262 ASIL-D parts run MBIST every power-on and periodically during idle, because a stuck cell in a safety-critical RAM is a fatal hazard. The controller typically adds ~2% area overhead per SRAM — cheap insurance.
Rule of thumb: If your design has more than ~100 kbit of embedded RAM, MBIST pays for itself in test time alone. For N-bit memories, budget 10N to 17N cycles depending on fault coverage needed (March C- = 10N, March SS for stuck-open faults = 22N).