A Fused Multiply-Add computes a * b + c as a single hardware operation with a single rounding at the end. The naive two-instruction sequence (tmp = a * b; result = tmp + c) rounds twice — once after the multiply, once after the add. FMA rounds once, so it's both faster and more accurate.

Why one rounding matters. The intermediate product a * b of two 53-bit mantissas (FP64) is a 106-bit number. A separate multiplier must truncate that to 53 bits before handing it to the adder, losing up to half an ULP. FMA keeps the full 106-bit product alive inside the unit, aligns it against c, then rounds the final 53-bit result. The accuracy gain is exploited by algorithms like Kahan summation, polynomial evaluation (Horner's method), and Newton-Raphson division — where compensated arithmetic relies on the exact unrounded product.

How the hardware fits. An FMA unit is basically a multiplier feeding an adder, but they share a datapath:

• Multiplier array (Wallace/Dadda tree) produces the 106-bit product in carry-save form — no final addition yet.
• Aligner shifts c to line up with the product's exponent. Because c's exponent can be wildly different, the aligner needs roughly a 3x-mantissa-width shifter.
• 3:2 carry-save adder merges the carry-save product with aligned c.
• Final adder + normalizer + rounder produces the IEEE-754 result.

Real-world example. Intel introduced FMA3 in Haswell (2013). An AVX-256 VFMADD231PD computes 4 FMAs (8 flops) per instruction with 5-cycle latency and 0.5-cycle throughput on Skylake — meaning 16 flops per cycle per core with two FMA units running in parallel. A 3.5 GHz Skylake core therefore peaks at ~56 GFLOPS FP64. Without FMA, you'd need separate multiply (3-cycle) and add (3-cycle) ops chained — doubling latency and halving peak throughput.

Rule of thumb. Modern HPC benchmarks (HPL/LINPACK) only hit advertised peak FLOPS by assuming every operation is an FMA. If your code is pure adds or pure multiplies, your effective peak is half the marketing number. To get full throughput, compilers fuse x*y + z patterns into FMAs — but only if you allow it (-ffp-contract=fast in GCC/Clang). Strict IEEE mode forbids the fusion because the result differs from the two-rounding version.

FMA also enables fast software division and square root via Newton-Raphson: each iteration is two FMAs, and the single-rounding property guarantees quadratic convergence to a correctly-rounded result.